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? freescale semiconductor, inc., 2004. all rights reserved. freescale semiconductor this hardware specification contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications for the mpc885/mpc880 (refer to table 1 for the list of devices). the mpc885 is the superset device of the mpc885/mpc880 family. the cpu on the mpc885/mpc880 is a 32-bit powerpc? core that incorporates memory management units (mmus) and instruction and data caches and that implements the powerpc instruction set. 1overview the mpc885/880 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. the mpc885/mpc880 provides enhanced atm functionality, an additional fast ethernet controller, a usb, and an encryption block. contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. maximum tolerated ratings . . . . . . . . . . . . . . . . . . . 9 4. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . 10 5. power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. thermal calculation and measurement . . . . . . . . . . 12 8. power supply and power sequencing . . . . . . . . . . . 14 9. layout practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10. bus signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11. ieee 1149.1 electrical specifications . . . . . . . . . . . 44 12. cpm electrical characteristics . . . . . . . . . . . . . . . . . 46 13. utopia ac electrical specifications . . . . . . . . . . . 69 15. fec electrical characteristics . . . . . . . . . . . . . . . . . 71 16. mechanical data and ordering information . . . . . . . 75 17. document revision history . . . . . . . . . . . . . . . . . . . 89 mpc885/mpc880 hardware specifications mpc885ec rev. 3, 07/2004
mpc885/mpc880 hardware specifications, rev. 3 2 freescale semiconductor features table 1 shows the functionality supported by the members of the mpc885 family. 2features the mpc885/880 is comprised of three modules that each use the 32-bit internal bus: a mpc8xx core, a system integration unit (siu), and a communications processor module (cpm). the following list summarizes the key mpc885/880 features: embedded mpc8xx core up to 133 mhz maximum frequency operation of the external bus is 80 mhz (in 1:1 mode) ? the 133-mhz core frequency supports 2:1 mode only. ? the 66-/80-mhz core frequencies support both the 1:1 and 2:1 modes. single-issue, 32-bit core (compatible with the powerpc architecture definition) with thirty-two 32-bit general-purpose registers (gprs) ? the core performs branch prediction with conditional prefetch and without conditional execution. ? 8-kbyte data cache and 8-kbyte instruction cache (see table 1 ) ? instruction cache is two-way, set-associative with 256 sets in 2 blocks ? data cache is two-way, set-associative with 256 sets ? cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. ? caches are physically addressed, implement a leas t recently used (lru) replacement algorithm, and are lockable on a cache block basis. ? mmus with 32-entry tlb, fully associative instruction and data tlbs ? mmus support multiple page sizes of 4, 16, and 512 kbytes, and 8 mbytes; 16 virtual address spaces and 16 protection groups ? advanced on-chip emulation debug mode provides enhanced atm functionality found on the mpc862 and mpc866 families and includes the following: ? improved operation, administration and maintenance (oam) support ? oam performance monitoring (pm) support ? multiple apc priority levels available to support a range of traffic pace requirements ? port-to-port switching capability without the need for ram-based microcode ? simultaneous mii (100baset) and utopia (half- or full -duplex) capability ? optional statistical cell counters per phy table 1. mpc885 family part cache ethernet scc smc usb atm support security engine i cache d cache 10baset 10/100 mpc885 8 kbyte 8 kbyte up to 3 2 3 2 1 serial atm and utopia interface yes mpc880 8 kbyte 8 kbyte up to 2 2 2 2 1 serial atm and utopia interface no
mpc885/mpc880 hardware specifications, rev. 3 freescale semiconductor 3 features ? utopia l2-compliant interface with added fifo buffering to reduce the total cell transmission time and multi-phy support. (the earlier utopia l1 specification is also supported.) ? parameter ram for both spi and i 2 c can be relocated without ram-based microcode ? supports full-duplex utopia master (atm side) and slave (phy side) operations using a split bus ? aal2/vbr functionality is rom-resident. up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines memory controller (eight banks) ? contains complete dynamic ram (dram) controller ? each bank can be a chip select or ras to support a dram bank. ? up to 30 wait states programmable per memory bank ? glueless interface to dram, simms, sram, eproms, flash eproms, and other memory devices ? dram controller programmable to support most size and speed memory interfaces ? four cas lines, four we lines, and one oe line ? boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) ? variable block sizes (32 kbyte?256 mbyte) ? selectable write protection ? on-chip bus arbitration logic general-purpose timers ? four 16-bit timers or two 32-bit timers ? gate mode can enable/disable counting. ? interrupt can be masked on reference match and event capture two fast ethernet controllers (fec)?two 10/100 mbps ethernet/ieee 802.3 cdma/cs that interface through mii and/or rmii interfaces system integration unit (siu) ? bus monitor ? software watchdog ? periodic interrupt timer (pit) ? clock synthesizer ? decrementer and time base ? reset controller ? ieee 1149.1 test access port (jtag) security engine is optimized to handle all the algorithms associated with ipsec, ssl/tls, srtp, 802.11i, and iscsi processing. available on the mpc885, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (chas). the chas are: ? data encryption standard execution unit (deu) ? des, 3des ? two key (k1, k2, k1) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des
mpc885/mpc880 hardware specifications, rev. 3 4 freescale semiconductor features ? advanced encryption standard unit (aesu) ? implements the rinjdael symmetric key cipher ? ecb, cbc, and counter modes ? 128-, 192-, and 256- bit key lengths ? message digest execution unit (mdeu) ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? crypto-channel supporting multi-command descriptor chains ? integrated controller managing internal resources and bus mastering ? buffer size of 256 bytes for the deu, aesu, and mdeu, with flow control for large data sizes interrupts ? six external interrupt request (irq) lines ? 12 port pins with interrupt capability ? 23 internal interrupt sources ? programmable priority between sccs ? programmable highest priority request communications processor module (cpm) ? risc controller ? communication-specific commands (for example, graceful stop transmit , enter hunt mode , and restart transmit ) ? supports continuous mode transmission and reception on all serial channels ? 8-kbytes of dual-port ram ? several serial dma (sdma) channels to support the cpm ? three parallel i/o registers with open-drain capability on-chip 16 16 multiply accumulate controller (mac) ? one operation per clock (two-clock latency, one-clock blockage) ? mac operates concurrently with other instructions ? fir loop?four clocks per four multiplies four baud rate generators ? independent (can be connected to any scc or smc) ? allow changes during operation ? autobaud support option up to three serial communication controllers (sccs) supporting the following protocols: ? serial atm capability on sccs ? optional utopia port on scc4 ? ethernet/ieee 802.3 optional on the scc(s) supporting full 10-mbps operation ? hdlc/sdlc ? hdlc bus (implements an hdlc-based local area network (lan)) ? asynchronous hdlc to support point-to-point protocol (ppp)
mpc885/mpc880 hardware specifications, rev. 3 freescale semiconductor 5 features ?appletalk ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? serial infrared (irda) ? binary synchronous communication (bisync) ? totally transparent (bit streams) ? totally transparent (frame based with optional cyclic redundancy check (crc)) up to two serial management channels (smcs) supporting the following protocols: ? uart (low-speed operation) ? transparent ? general circuit interface (gci) controller ? provide management for bri devices as gci controller in time-division multiplexed (tdm) channels universal serial bus (usb)?supports operation as a usb function endpoint, a usb host controller, or both for testing purposes (loop-back diagnostics) ? usb 2.0 full-/low-speed compatible ? the usb function mode has the following features: ? four independent endpoints support control, bulk, interrupt, and isochronous data transfers. ? crc16 generation and checking ? crc5 checking ? nrzi encoding/decoding with bit stuffing ? 12- or 1.5-mbps data rate ? flexible data buffers with multiple buffers per frame ? automatic retransmission upon transmit error ? the usb host controller has the following features: ? supports control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? nrzi encoding/decoding with bit stuffing ? supports both 12- and 1.5-mbps data rates (automatic generation of preamble token and data rate configuration). note that low-speed operation requires an external hub. ? flexible data buffers with multiple buffers per frame ? supports local loop back mode for diagnostics (12 mbps only) serial peripheral interface (spi) ? supports master and slave modes ? supports multiple-master operation on the same bus inter-integrated circuit (i 2 c) port ? supports master and slave modes ? supports a multiple-master environment time-slot assigner (tsa) ? allows sccs and smcs to run in multiplexed and/or non-multiplexed operation ? supports t1, cept, pcm highway, isdn basic rate, isdn primary rate, user defined
mpc885/mpc880 hardware specifications, rev. 3 6 freescale semiconductor features ? 1- or 8-bit resolution ? allows independent transmit and receive routing, frame synchronization, and clocking ? allows dynamic changes ? can be internally connected to four serial channels (two sccs and two smcs) parallel interface port (pip) ? centronics interface support ? supports fast connection between compatible ports on mpc885/880 and other mpc8xx devices pcmcia interface ? master (socket) interface, release 2.1-compliant ? supports two independent pcmcia sockets ? 8 memory or i/o windows supported debug interface ? eight comparators: four operate on instruction address, two operate on data address, and two operate on data ? supports conditions: = < > ? each watchpoint can generate a break point internally. normal high and normal low power modes to conserve power 1.8-v core and 3.3-v i/o operation the mpc885/880 comes in a 357-pin ball grid array (pbga) package.
mpc885/mpc880 hardware specifications, rev. 3 freescale semiconductor 7 features the mpc885 block diagram is shown in figure 1 . figure 1. mpc885 block diagram bus system interface unit (siu) embedded parallel i/o memory controller 4 timers interrupt controllers 8-kbyte dual-port ram system functions 8-kbyte instruction cache 32-entry itlb instruction mmu 8-kbyte data cache 32-entry dtlb data mmu instruction bus load/store bus unified 4 baud rate generators parallel interface port internal bus interface unit external bus interface unit timers 32-bit risc controller and program rom serial interface i 2 c spi smc2 smc1 mpc8xx processor core scc2 serial interface pcmcia-ata interface virtual idma and serial dmas scc4/ security engine aesu deu mdeu controller channel dmas fifos 10/100 miii/rmii baset media access control fast ethernet controller utopia scc3 usb slave/master if time slot assigner dmas
mpc885/mpc880 hardware specifications, rev. 3 8 freescale semiconductor features the mpc880 block diagram is shown in figure 2 . figure 2. mpc880 block diagram bus system interface unit (siu) embedded parallel i/o memory controller 4 timers interrupt controllers 8-kbyte dual-port ram system functions 8-kbyte instruction cache 32-entry itlb instruction mmu 8-kbyte data cache 32-entry dtlb data mmu instruction bus load/store bus unified 4 baud rate generators parallel interface port internal bus interface unit external bus interface unit timers 32-bit risc controller and program rom serial interface i 2 c spi smc2 smc1 mpc8xx processor core scc3 serial interface pcmcia-ata interface virtual idma and serial dmas scc4/ dmas fifos 10/100 miii/rmii baset media access control fast ethernet controller utopia usb slave/master if time slot assigner dmas
mpc885/mpc880 hardware specifications, rev. 3 freescale semiconductor 9 maximum tolerated ratings 3 maximum tolerated ratings this section provides the maximum tolerated voltage and temperature ranges for the mpc885/880. table 2 displays the maximum tolerated ratings, and table 3 displays the operating temperatures. this device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v dd ). table 2. maximum tolerated ratings rating symbol value unit supply voltage 1 1 the power supply of the device must start its ramp from 0.0 v. v ddh ?0.3 to 4.0 v v ddl ?0.3 to 2.0 v vddsyn ?0.3 to 2.0 v difference between v ddl and v ddsyn <100 mv input voltage 2 2 functional operating conditions are provided with the dc electrical specifications in tab l e 6 . absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. see section 8, ?power supply and power sequencing .? caution : all inputs that tolerate 5 v cannot be more than 2.5 v greater than vddh. this restriction applies to power up and normal operation (that is, if the mpc885/880 is unpowered, a voltage greater than 2.5 v must not be applied to its inputs). v in gnd ? 0.3 to v ddh v storage temperature range t stg ?55 to +150 c table 3. operating temperatures rating symbol value unit temperature 1 (standard) 1 minimum temperatures are guaranteed as ambient temperature, t a . maximum temperatures are guaranteed as junction temperature, t j . t a(min) 0c t j(max) 95 c temperature (extended) t a(min) ?40 c t j(max) 100 c
mpc885/mpc880 hardware specifications, rev. 3 10 freescale semiconductor thermal characteristics 4 thermal characteristics table 4 shows the thermal characteristics for the mpc885/880. 5 power dissipation table 5 provides information on power dissipation. the modes are 1:1, where cpu and bus speeds are equal, and 2:1, where cpu frequency is twice bus speed. table 4. mpc885/880 thermal resistance data rating environment symbol value unit junction-to-ambient 1 1 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipat ion of other components on the board, and board thermal resistance. natural convection single-layer board (1s) r ja 2 2 per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 37 c/w four-layer board (2s2p) r jma 3 3 per jedec jesd51-6 with the board horizontal 25 airflow (200 ft/min) single-layer board (1s) r jma 3 30 four-layer board (2s2p) r jma 3 22 junction-to-board 4 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb 17 junction-to-case 5 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. for exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. r jc 10 junction-to-package top 6 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. natural convection jt 2 airflow (200 ft/min) jt 2 table 5. power dissipation (p d ) die revision bus mode cpu frequency typical 1 1 typical power dissipation at v ddl = v ddsyn = 1.8 v, and v ddh is at 3.3 v. maximum 2 unit 0 1:1 66 mhz 310 390 mw 80 mhz 350 430 mw 2:1 133 mhz 430 495 mw
mpc885/mpc880 hardware specifications, rev. 3 freescale semiconductor 11 dc characteristics 6 dc characteristics table 6 provides the dc electrical characteristics for the mpc885/880. 2 maximum power dissipation at v ddl = v ddsyn = 1.9 v, and v ddh is at 3.5 v. note the values in table 5 represent v ddl -based power dissipation and do not include i/o power dissipation over v ddh . i/o power dissipation varies widely by application due to buffer current, depending on external circuitry. the v ddsyn power dissipation is negligible. table 6. dc electrical specifications characteristic symbol min max unit operating voltage v ddl (core) 1.7 1.9 v v ddh (i/o) 3.135 3.465 v v ddsyn 1 1 the difference between v ddl and v ddsyn cannot be more than 100 mv. 1.7 1.9 v difference between v ddl and v ddsyn ? 100 mv input high voltage (all inputs except extal and extclk) 2 2 the signals pa[0:15], pb[14:31], pc[4:15], pd [3:15], pe(14:31), tdi, tdo, tck, trst , tms, mii1_txen, mii_mdio are 5-v tolerant. the minimum voltage is still 2.0 v. v ih 2.0 3.465 v input low voltage 3 3 v il (max) for the i 2 c interface is 0.8 v rather than the 1.5 v as specified in the i 2 c standard. v il gnd 0.8 v extal, extclk input high voltage v ihc 0.7*(v dd h ) v ddh v input leakage current, vin = 5.5 v (except tms, trst , dsck and dsdi pins) for 5-v tolerant pins 2 i in ? 100 a input leakage current, vin = v ddh (except tms, trst , dsck, and dsdi) i in ?10a input leakage current, vin = 0 v (except tms, trst , dsck and dsdi pins) i in ?10a input capacitance 4 c in ?20pf output high voltage, ioh = ?2.0 ma, except xtal and open-drain pins v oh 2.4 ? v output low voltage iol = 2.0 ma (clkout) iol = 3.2 ma 5 iol = 5.3 ma 6 iol = 7.0 ma (txd1/pa14, txd2/pa12) iol = 8.9 ma (ts , ta , tea , bi , bb , hreset , sreset ) v ol ?0.5 v
mpc885/mpc880 hardware specifications, rev. 3 12 freescale semiconductor thermal calculation and measurement 7 thermal calculation and measurement for the following discussions, p d = (v ddl i ddl ) + pi/o, where pi/o is the power dissipation of the i/o drivers. note the v ddsyn power dissipation is negligible. 7.1 estimation with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , in c can be obtained from the following equation: t j = t a + (r ja p d ) where: t a = ambient temperature oc r ja = package junction-to-ambient thermal resistance (oc/w) p d = power dissipation in package the junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. however, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity t j ?t a ) are possible. 7.2 estimation with junction-to-case thermal resistance historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance (oc/w) r jc = junction-to-case thermal resistance (oc/w) r ca = case-to-ambient thermal resistance (oc/w) r jc is device-related and cannot be influenced by the user. the user adjusts the thermal environment to affect the case-to-ambient thermal resistance, r ca . for instance, the user can change the airflow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. for most packages, a better model is required. 4 input capacitance is periodically sampled. 5 a(0:31), tsiz0/reg , tsiz1, d(0:31), irq (2:4), irq6 , rd/wr , burst , ip_b(3:7), pa(0:11), pa13, pa15, pb(14:31), pc(4:15), pd(3:15), pe(14:31), mii1_crs, mii_mdio, mii1_txen, mii1_col. 6 bdip /gpl_b (5), br , bg , frz/irq6 , cs (0:7), we (0:3), bs _a(0:3), gpl_a0 /gpl_b0 , oe /gpl_a1 /gpl_b1 , gpl_a (2:3)/gpl_b (2:3)/cs (2:3), upwaita/gpl_a4 , upwaitb/gpl_b4 , gpl_a5 , ale_a, ce 1_a, ce 2_a, op(0:3) baddr(28:30)
mpc885/mpc880 hardware specifications, rev. 3 freescale semiconductor 13 thermal calculation and measurement 7.3 estimation with junction-to-board thermal resistance a simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. the junction-to-case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. it has been observed that the thermal performance of most plastic packages and especially pbga packages is strongly dependent on the board temperature; see figure 3 . figure 3. effect of board temperature rise on thermal behavior if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b + (r jb p d ) where: r jb = junction-to-board thermal resistance (oc/w) t b = board temperature oc p d = power dissipation in package if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. for this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 estimation using simulation when the board temperature is not known, a thermal simulation of the application is needed. the simple two resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation.
mpc885/mpc880 hardware specifications, rev. 3 14 freescale semiconductor power supply and power sequencing 7.5 experimental determination to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d ) where: jt = thermal characterization parameter t t = thermocouple temperature on top of package p d = power dissipation in package the thermal characterization parameter is measured per the jesd51-2 specification published by jedec using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. 7.6 references semiconductor equipment and materials international (415) 964-5111 805 east middlefield rd mountain view, ca 94043 mil-spec and eia/jesd (jedec) specifications 800-854-7179 or (available from global engineering documents) 303-397-7956 jedec specifications http://www.jedec.org 1. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semitherm, san diego, 1998, pp. 47-54. 2. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of semitherm, san diego, 1999, pp. 212-220. 8 power supply and power sequencing this section provides design considerations for the mpc885/880 power supply. the mpc885/880 has a core voltage (v ddl ) and pll voltage (v ddsyn ), which both operate at a lower voltage than the i/o voltage v ddh . the i/o section of the mpc885/880 is supplied with 3.3 v across v ddh and v ss (gnd). the signals pa[0:15], pb[14:31], pc[4:15], pd[3:15], tdi, tdo, tck, trst_b, tms, mii_txen, and mii_mdio are 5-v tolerant. all inputs cannot be more than 2.5 v greater than v ddh . in addition, 5-v tolerant pins can not exceed 5.5 v and remaining input pins cannot exceed 3.465 v. this restriction applies to power up/down and normal operation. one consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different rates. the rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. the following restrictions apply: v ddl must not exceed v ddh during power up and power down. v ddl must not exceed 1.9 v, and v ddh must not exceed 3.465 v.
mpc885/mpc880 hardware specifications, rev. 3 15 freescale semiconductor layout practices these cautions are necessary for the long-term reliability of the part. if they are violated, the electrostatic discharge (esd) protection diodes are forward-biased, and excessive current can flow through these diodes. if the system power supply design does not control the voltage sequencing, the circuit shown figure 4 can be added to meet these requirements. the mur420 schottky diodes control the maximum potential difference between the external bus and core power supplies on power up, and the 1n5820 diodes regulate the maximum potential difference on power down. figure 4. example voltage sequencing circuit 9 layout practices each v dd pin on the mpc885/880 should be provided with a low-impedance path to the board?s supply. each gnd pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v dd power supply should be bypassed to ground using at least four 0.1 f by-pass capacitors located as close as possible to the four sides of the package. each board designed should be characterized and additional appropriate decoupling capacitors should be used if required. the capacitor leads and associated printed circuit traces connecting to chip v dd and gnd should be kept to less than half an inch per capacitor lead. at a minimum, a four-layer board employing two inner layers as v dd and gnd planes should be used. all output pins on the mpc885/880 have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v dd and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. for more information, please refer to the mpc885 user?s manual , section 14.4.3, ?clock synthesizer power (v ddsyn , v sssyn , v sssyn1 )?. 10 bus signal timing the maximum bus speed supported by the mpc885/880 is 80 mhz. higher-speed parts must be operated in half-speed bus mode (for example, an mpc885/880 used at 133 mhz must be configured for a 66 mhz bus). table 7 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and table 8 shows the frequency ranges for standard part frequencies in 2:1 bus mode. v ddh v ddl 1n5820 mur420
mpc885/mpc880 hardware specifications, rev. 3 16 freescale semiconductor bus signal timing table 9 provides the timings for the mpc885/880 at 33-, 40-, 66-, and 80-mhz bus operation. the timing for the mpc885/880 bus shown assumes a 50-pf load for maximum delays and a 0-pf load for minimum delays. clkout assumes a 100-pf load maximum delay. table 7. frequency ranges for standard part frequencies (1:1 bus mode) part frequency 66 mhz 80 mhz min max min max core frequency 40 66.67 40 80 bus frequency 40 66.67 40 80 table 8. frequency ranges for standard part frequencies (2:1 bus mode) part frequency 66 mhz 80 mhz 133 mhz min max min max min max core frequency 40 66.67 40 80 40 133 bus frequency 20 33.33 20 40 20 66 table 9. bus operation timings num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max b1 bus period (clkout), see ta bl e 7 ????????ns b1a extclk to clkout phase skew - if clkout is an integer multiple of extclk, then the rising edge of extclk is aligned with the rising edge of clkout. for a non-integer multiple of extclk, this synchronization is lost, and the rising edges of extclk and clkout have a continuously varying phase skew. ?2 +2 ?2 +2 ?2 +2 ?2 +2 ns b1b clkout frequency jitter peak-to-peak ? 1 ? 1 ? 1 ? 1 ns b1c frequency jitter on extclk ? 0.50 ? 0.50 ? 0.50 ? 0.50 % b1d clkout phase jitter peak-to-peak for osclk 15 mhz ?4?4?4?4ns clkout phase jitter peak-to-peak for osclk < 15 mhz ?5 ? 5?5?5ns b2 clkout pulse width low (min = 0.4 b1, max = 0.6 b1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns b3 clkout pulse width high (min = 0.4 b1, max = 0.6 b1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns b4 clkout rise time ? 4.00 ? 4.00 ? 4.00 ? 4.00 ns b5 clkout fall time ? 4.00 ? 4.00 ? 4.00 ? 4.00 ns
mpc885/mpc880 hardware specifications, rev. 3 17 freescale semiconductor bus signal timing b7 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31) output hold (min = 0.25 b1) 7.60 ? 6.30 ? 3.80 ? 3.13 ? ns b7a clkout to tsiz(0:1), reg , rsv , bdip , ptr output hold (min = 0.25 b1) 7.60 ? 6.30 ? 3.80 ? 3.13 ? ns b7b clkout to br , bg , frz, vfls(0:1), vf(0:2) iwp(0:2), lwp(0:1), sts output hold (min = 0.25 b1) 7.60 ? 6.30 ? 3.80 ? 3.13 ? ns b8 clkout to a(0:31), baddr(28:30) rd/wr , burst , d(0:31) valid (max = 0.25 b1 + 6.3) ?13.80?12.50?10.00? 9.43 ns b8a clkout to tsiz(0:1), reg , rsv , at(0:3) bdip , ptr valid (max = 0.25 b1 + 6.3) ?13.80?12.50?10.00? 9.43 ns b8b clkout to br , bg , vfls(0:1), vf(0:2), iwp(0:2), frz, lwp(0:1), sts valid 4 (max = 0.25 b1 + 6.3) ?13.80?12.50?10.00? 9.43 ns b9 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31), tsiz(0:1), reg , rsv , at(0:3), ptr high-z (max = 0.25 b1 + 6.3) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns b11 clkout to ts , bb assertion (max = 0.25 b1 + 6.0) 7.60 13.60 6.30 12.30 3.80 9.80 3.13 9.13 ns b11a clkout to ta , bi assertion (when driven by the memory controller or pcmcia interface) (max = 0.00 b1 + 9.30 1 ) 2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.30 ns b12 clkout to ts , bb negation (max = 0.25 b1 + 4.8) 7.60 12.30 6.30 11.00 3.80 8.50 3.13 7.92 ns b12a clkout to ta , bi negation (when driven by the memory controller or pcmcia interface) (max = 0.00 b1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.5 9.00 ns b13 clkout to ts , bb high-z (min = 0.25 b1) 7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 ns b13a clkout to ta , bi high-z (when driven by the memory controller or pcmcia interface) (min = 0.00 b1 + 2.5) 2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns b14 clkout to tea assertion (max = 0.00 b1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns b15 clkout to tea high-z (min = 0.00 b1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns b16 ta , bi valid to clkout (setup time) (min = 0.00 b1 + 6.00) 6.00 ? 6.00 ? 6.00 ? 6 ? ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc885/mpc880 hardware specifications, rev. 3 18 freescale semiconductor bus signal timing b16a tea , kr , retry , cr valid to clkout (setup time) (min = 0.00 b1 + 4.5) 4.50 ? 4.50 ? 4.50 ? 4.50 ? ns b16b bb , bg , br , valid to clkout (setup time) 2 (4min = 0.00 b1 + 0.00) 4.00 ? 4.00 ? 4.00 ? 4.00 ? ns b17 clkout to ta , tea , bi , bb , bg , br valid (hold time) (min = 0.00 b1 + 1.00 3 ) 1.00 ? 1.00 ? 2.00 ? 2.00 ? ns b17a clkout to kr , retry , cr valid (hold time) (min = 0.00 b1 + 2.00) 2.00 ? 2.00 ? 2.00 ? 2.00 ? ns b18 d(0:31) valid to clkout rising edge (setup time) 4 (min = 0.00 b1 + 6.00) 6.00 ? 6.00 ? 6.00 ? 6.00 ? ns b19 clkout rising edge to d(0:31) valid (hold time) 4 (min = 0.00 b1 + 1.00 5 ) 1.00 ? 1.00 ? 2.00 ? 2.00 ? ns b20 d(0:31) valid to clkout falling edge (setup time) 6 (min = 0.00 b1 + 4.00) 4.00 ? 4.00 ? 4.00 ? 4.00 ? ns b21 clkout falling edge to d(0:31) valid (hold time) 6 (min = 0.00 b1 + 2.00) 2.00 ? 2.00 ? 2.00 ? 2.00 ? ns b22 clkout rising edge to cs asserted gpcm acs = 00 (max = 0.25 b1 + 6.3) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns b22a clkout falling edge to cs asserted gpcm acs = 10, trlx = 0 (max = 0.00 b1 + 8.00) ? 8.00 ? 8.00 ? 8.00 ? 8.00 ns b22b clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 0 (max = 0.25 b1 + 6.3) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns b22c clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 1 (max = 0.375 b1 + 6.6) 10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns b23 clkout rising edge to cs negated gpcm read access, gpcm write access acs = 00, trlx = 0 and csnt = 0 (max = 0.00 b1 + 8.00) 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns b24 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 0 (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b24a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11 trlx = 0 (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b25 clkout rising edge to oe , we (0:3) asserted (max = 0.00 b1 + 9.00) ? 9.00 ? 9.00 ? 9.00 ? 9.00 ns b26 clkout rising edge to oe negated (max = 0.00 b1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc885/mpc880 hardware specifications, rev. 3 19 freescale semiconductor bus signal timing b27 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 1 (min = 1.25 b1 ? 2.00) 35.90 ? 29.30 ? 16.90 ? 13.60 ? ns b27a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 1 (min = 1.50 b1 ? 2.00) 43.50 ? 35.50 ? 20.70 ? 16.75 ? ns b28 clkout rising edge to we (0:3) negated gpcm write access csnt = 0 (max = 0.00 b1 + 9.00) ? 9.00 ? 9.00 ? 9.00 ? 9.00 ns b28a clkout falling edge to we (0:3) negated gpcm write access trlx = 0, csnt = 1, ebdf = 0 (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns b28b clkout falling edge to cs negated gpcm write access trlx = 0, csnt = 1 acs = 10 or acs = 11, ebdf = 0 (max = 0.25 b1 + 6.80) ?14.30?13.00?10.50? 9.93 ns b28c clkout falling edge to we (0:3) negated gpcm write access trlx = 0, csnt = 1 write access trlx = 0, csnt = 1, ebdf = 1 (max = 0.375 b1 + 6.6) 10.90 18.00 10.90 18.00 5.20 12.30 4.69 11.29 ns b28d clkout falling edge to cs negated gpcm write access trlx = 0, csnt = 1, acs = 10, or acs = 11, ebdf = 1 (max = 0.375 b1 + 6.6) ? 18.00 ? 18.00 ? 12.30 ? 11.30 ns b29 we (0:3) negated to d(0:31) high-z gpcm write access, csnt = 0, ebdf = 0 (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b29a we (0:3) negated to d(0:31) high-z gpcm write access, trlx = 0, csnt = 1, ebdf = 0 (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b29b cs negated to d(0:31) high-z gpcm write access, acs = 00, trlx = 0 & csnt = 0 (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b29c cs negated to d(0:31) high-z gpcm write access, trlx = 0, csnt = 1, acs = 10, or acs = 11 ebdf = 0 (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b29d we (0:3) negated to d(0:31) high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 0 (min = 1.50 b1 ? 2.00) 43.50 ? 35.50 ? 20.70 ? 16.75 ? ns b29e cs negated to d(0:31) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10, or acs = 11 ebdf = 0 (min = 1.50 b1 ? 2.00) 43.50 ? 35.50 ? 20.70 ? 16.75 ? ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc885/mpc880 hardware specifications, rev. 3 20 freescale semiconductor bus signal timing b29f we (0:3) negated to d(0:31) high-z gpcm write access, trlx = 0, csnt = 1, ebdf = 1 (min = 0.375 b1 ? 6.30) 5.00 ? 3.00 ? 0.00 ? 0.00 ? ns b29g cs negated to d(0:31) high-z gpcm write access, trlx = 0, csnt = 1 acs = 10 or acs = 11, ebdf = 1 (min = 0.375 b1?6.30) 5.00 ? 3.00 ? 0.00 ? 0.00 ? ns b29h we (0:3) negated to d(0:31) high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 1 (min = 0.375 b1 ? 3.30) 38.40 ? 31.10 ? 17.50 ? 13.85 ? ns b29i cs negated to d(0:31) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 1 (min = 0.375 b1?3.30) 38.40 ? 31.10 ? 17.50 ? 13.85 ? ns b30 cs , we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access 7 (min = 0.25 b1?.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b30a we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm, write access, trlx = 0, csnt = 1, cs negated to a(0:31) invalid gpcm write access trlx = 0, csnt =1 acs = 10, or acs == 11, ebdf = 0 (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b30b we (0:3) negated to a(0:31) invalid gpcm baddr(28:30) invalid gpcm write access, trlx = 1, csnt = 1. cs negated to a(0:31) invalid gpcm write access trlx = 1, csnt = 1, acs = 10, or acs == 11 ebdf = 0 (min = 1.50 b1 ? 2.00) 43.50 ? 35.50 ? 20.70 ? 16.75 ? ns b30c we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx = 0, csnt = 1. cs negated to a(0:31) invalid gpcm write access, trlx = 0, csnt = 1 acs = 10, acs == 11, ebdf = 1 (min = 0.375 b1?3.00) 8.40 ? 6.40 ? 2.70 ? 1.70 ? ns b30d we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access trlx = 1, csnt =1, cs negated to a(0:31) invalid gpcm write access trlx = 1, csnt = 1, acs = 10 or 11, ebdf = 1 38.67 ? 31.38 ? 17.83 ? 14.19 ? ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc885/mpc880 hardware specifications, rev. 3 21 freescale semiconductor bus signal timing b31 clkout falling edge to cs valid, as requested by control bit cst4 in the corresponding word in the upm (max = 0.00 b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b31a clkout falling edge to cs valid, as requested by control bit cst1 in the corresponding word in the upm (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns b31b clkout rising edge to cs valid, as requested by control bit cst2 in the corresponding word in the upm (max = 0.00 b1 + 8.00) 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns b31c clkout rising edge to cs valid, as requested by control bit cst3 in the corresponding word in the upm (max = 0.25 b1 + 6.30) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns b31d clkout falling edge to cs valid, as requested by control bit cst1 in the corresponding word in the upm ebdf = 1 (max = 0.375 b1 + 6.6) 13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30 ns b32 clkout falling edge to bs valid, as requested by control bit bst4 in the corresponding word in the upm (max = 0.00 b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b32a clkout falling edge to bs valid, as requested by control bit bst1 in the corresponding word in the upm, ebdf = 0 (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns b32b clkout rising edge to bs valid, as requested by control bit bst2 in the corresponding word in the upm (max = 0.00 b1 + 8.00) 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns b32c clkout rising edge to bs valid, as requested by control bit bst3 in the corresponding word in the upm (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns b32d clkout falling edge to bs valid, as requested by control bit bst1 in the corresponding word in the upm, ebdf = 1 (max = 0.375 b1 + 6.60) 13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30 ns b33 clkout falling edge to gpl valid, as requested by control bit gxt4 in the corresponding word in the upm (max = 0.00 b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc885/mpc880 hardware specifications, rev. 3 22 freescale semiconductor bus signal timing b33a clkout rising edge to gpl valid, as requested by control bit gxt3 in the corresponding word in the upm (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns b34 a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by control bit cst4 in the corresponding word in the upm (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b34a a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by control bit cst1 in the corresponding word in the upm (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b34b a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by cst2 in the corresponding word in upm (min = 0.75 b1 ? 2.00) 20.70 ? 16.70 ? 9.40 ? 6.80 ? ns b35 a(0:31), baddr(28:30) to cs valid, as requested by control bit bst4 in the corresponding word in the upm (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b35a a(0:31), baddr(28:30), and d(0:31) to bs valid, as requested by bst1 in the corresponding word in the upm (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b35b a(0:31), baddr(28:30), and d(0:31) to bs valid, as requested by control bit bst2 in the corresponding word in the upm (min = 0.75 b1 ? 2.00) 20.70 ? 16.70 ? 9.40 ? 7.40 ? ns b36 a(0:31), baddr(28:30), and d(0:31) to gpl valid, as requested by control bit gxt4 in the corresponding word in the upm (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b37 upwait valid to clkout falling edge 8 (min = 0.00 b1 + 6.00) 6.00 ? 6.00 ? 6.00 ? 6.00 ? ns b38 clkout falling edge to upwait valid 8 (min = 0.00 b1 + 1.00) 1.00 ? 1.00 ? 1.00 ? 1.00 ? ns b39 as valid to clkout rising edge 9 (min = 0.00 b1 + 7.00) 7.00 ? 7.00 ? 7.00 ? 7.00 ? ns b40 a(0:31), tsiz(0:1), rd/wr , burst , valid to clkout rising edge (min = 0.00 b1 + 7.00) 7.00 ? 7.00 ? 7.00 ? 7.00 ? ns b41 ts valid to clkout rising edge (setup time) (min = 0.00 b1 + 7.00) 7.00 ? 7.00 ? 7.00 ? 7.00 ? ns table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc885/mpc880 hardware specifications, rev. 3 23 freescale semiconductor bus signal timing b42 clkout rising edge to ts valid (hold time) (min = 0.00 b1 + 2.00) 2.00 ? 2.00 ? 2.00 ? 2.00 ? ns b43 as negation to memory controller signals negation (max = tbd) ?tbd?tbd?tbd?tbdns 1 for part speeds above 50 mhz, use 9.80 ns for b11a. 2 the timing required for br input is relevant when the mpc885/880 is selected to work with the internal bus arbiter. the timing for bg input is relevant when the mpc885/880 is selected to work with the external bus arbiter. 3 for part speeds above 50 mhz, use 2 ns for b17. 4 the d(0:31) input timings b18 and b19 refer to the rising edge of the clkout in which the ta input signal is asserted. 5 for part speeds above 50 mhz, use 2 ns for b19. 6 the d(0:31) input timings b20 and b21 refer to the falling edge of the clkout. this timing is valid only for read accesses controlled by chip-selects under control of the user-programmable machine (upm) in the memory controller, for data beats where dlt3 = 1 in the ram words. (this is only the case where data is latched on the falling edge of clkout.) 7 the timing b30 refers to cs when acs = 00 and to we (0:3) when csnt = 0. 8 the signal upwait is considered asynchronous to the clkout and synchronized internally. the timings specified in b37 and b38 are specified to enable the freeze of the upm output signals as described in figure 20 . 9 the as signal is considered asynchronous to the clkout. the timing b39 is specified in order to allow the behavior specified in figure 23 . table 9. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc885/mpc880 hardware specifications, rev. 3 24 freescale semiconductor bus signal timing figure 5 provides the control timing diagram. figure 5. control timing figure 6 provides the timing for the external clock. figure 6. external clock timing clkout outputs a b 2.0 v 0.8 v 0.8 v 2.0 v 2.0 v 0.8 v 2.0 v 0.8 v outputs 2.0 v 0.8 v 2.0 v 0.8 v b a inputs 2.0 v 0.8 v 2.0 v 0.8 v d c inputs 2.0 v 0.8 v 2.0 v 0.8 v c d a maximum output delay specification b minimum output hold time c minimum input setup time specification d minimum input hold time specification clkout b1 b5 b3 b4 b1 b2
mpc885/mpc880 hardware specifications, rev. 3 25 freescale semiconductor bus signal timing figure 7 provides the timing for the synchronous output signals. figure 7. synchronous output signals timing figure 8 provides the timing for the synchronous active pull-up and open-drain output signals. figure 8. synchronous active pull-up resistor and open-drain outputs signals timing clkout output signals output signals output signals b8 b7 b9 b8a b9 b7a b8b b7b clkout ts , bb ta , bi tea b13 b12 b11 b11 b12 b13 b15 b14
mpc885/mpc880 hardware specifications, rev. 3 26 freescale semiconductor bus signal timing figure 9 provides the timing for the synchronous input signals. figure 9. synchronous input signals timing figure 10 provides normal case timing for input data. it also applies to normal read accesses under the control of the user-programmable machine (upm) in the memory controller. figure 10. input data timing in normal case clkout ta , bi tea , kr , retry , cr bb , bg , br b16 b17 b16 b17 b16 b17 clkout ta d[0:31] b16 b17 b19 b18
mpc885/mpc880 hardware specifications, rev. 3 27 freescale semiconductor bus signal timing figure 11 provides the timing for the input data controlled by the upm for data beats where dlt3 = 1 in the upm ram words. (this is only the case where data is latched on the falling edge of clkout.) figure 11. input data timing when controlled by upm in the memory controller and dlt3 = 1 figure 12 through figure 15 provide the timing for the external bus read controlled by various gpcm factors. figure 12. external bus read timing (gpcm controlled?acs = 00) clkout ta d[0:31] b20 b21 clkout a[0:31] cs x oe we [0:3] ts d[0:31] b11 b12 b23 b8 b22 b26 b19 b18 b25 b28
mpc885/mpc880 hardware specifications, rev. 3 28 freescale semiconductor bus signal timing figure 13. external bus read timing (gpcm controlled?trlx = 0, acs = 10) figure 14. external bus read timing (gpcm controlled?trlx = 0, acs = 11) clkout a[0:31] cs x oe ts d[0:31] b11 b12 b8 b22 b23 b26 b19 b18 b25 b24 clkout a[0:31] cs x oe ts d[0:31] b11 b12 b22 b8 b22 b23 b24 b25 b26 b19 b18
mpc885/mpc880 hardware specifications, rev. 3 29 freescale semiconductor bus signal timing figure 15. external bus read timing (gpcm controlled?trlx = 1, acs = 10, acs = 11) clkout a[0:31] cs x oe ts d[0:31] b11 b12 b8 b22 b27 b27 b22 b22 b19 b18 b26 b23
mpc885/mpc880 hardware specifications, rev. 3 30 freescale semiconductor bus signal timing figure 16 through figure 18 provide the timing for the external bus write controlled by various gpcm factors. figure 16. external bus write timing (gpcm controlled?trlx = 0, csnt = 0) clkout a[0:31] cs x we [0:3] oe ts d[0:31] b11 b8 b22 b23 b12 b30 b28 b25 b26 b8 b9 b29 b29
mpc885/mpc880 hardware specifications, rev. 3 31 freescale semiconductor bus signal timing figure 17. external bus write timing (gpcm controlled?trlx = 0, csnt = 1) b23 b30 b30 clkout a[0:31] cs x oe we [0:3] ts d[0:31] b11 b8 b22 b12 b28 b28 b25 b26 b8 b28 b9 b28 b29 b29 b29 b29f
mpc885/mpc880 hardware specifications, rev. 3 32 freescale semiconductor bus signal timing figure 18. external bus write timing (gpcm controlled?trlx = 1, csnt = 1) b23 b22 b8 b12 b11 clkout a[0:31] cs x we [0:3] ts oe d[0:31] b30 b30 b28 b28 b25 b29 b29i b26 b29 b29 b28 b28 b9 b8 b29
mpc885/mpc880 hardware specifications, rev. 3 33 freescale semiconductor bus signal timing figure 19 provides the timing for the external bus controlled by the upm. figure 19. external bus timing (upm-controlled signals) clkout cs x b31 b8 b31 b34 b32 gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] a[0:31] b31 b31 b34 b32 b32 b32 b34 b36 b35 b35 b35 b33 b32 b33 b31
mpc885/mpc880 hardware specifications, rev. 3 34 freescale semiconductor bus signal timing figure 20 provides the timing for the asynchronous asserted upwait signal controlled by the upm. figure 20. asynchronous upwait asserted detection in upm-handled cycles timing figure 21 provides the timing for the asynchronous negated upwait signal controlled by the upm. figure 21. asynchronous upwait negated detection in upm-handled cycles timing clkout cs x upwait gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] b37 b38 clkout cs x upwait gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] b37 b38
mpc885/mpc880 hardware specifications, rev. 3 35 freescale semiconductor bus signal timing figure 22 provides the timing for the synchronous external master access controlled by the gpcm. figure 22. synchronous external master access timing (gpcm handled?acs = 00) figure 23 provides the timing for the asynchronous external master memory access controlled by the gpcm. figure 23. asynchronous external master memory access timing (gpcm controlled?acs = 00) figure 24 provides the timing for the asynchronous external master control signals negation. figure 24. asynchronous external master?control signals negation timing clkout ts a[0:31], tsiz[0:1], r/w , burst cs x b41 b42 b40 b22 clkout as a[0:31], tsiz[0:1], r/w cs x b39 b40 b22 as cs x, we [0:3], oe , gplx , bs [0:3] b43
mpc885/mpc880 hardware specifications, rev. 3 36 freescale semiconductor bus signal timing table 10 provides the interrupt timing for the mpc885/880. figure 25 provides the interrupt detection timing for the external level-sensitive lines. figure 25. interrupt detection timing for external level sensitive lines figure 26 provides the interrupt detection timing for the external edge-sensitive lines. figure 26. interrupt detection timing for external edge sensitive lines table 10. interrupt timing num characteristic 1 1 the i39 and i40 timings describe the testing conditions under which the irq lines are tested when being defined as level sensitive. the irq lines are synchronized internally and do not have to be asserted or negated with reference to the clkout. the i41, i42, and i43 timings are specified to allow correct functioning of the irq lines detection circuitry and have no direct relation with the total system interrupt latency that the mpc885/880 is able to support. all frequencies unit min max i39 irq x valid to clkout rising edge (setup time) 6.00 ns i40 irq x hold time after clkout 2.00 ns i41 irq x pulse width low 3.00 ns i42 irq x pulse width high 3.00 ns i43 irq x edge-to-edge time 4 t clockout ? clkout irq x i39 i40 clkout irq x i41 i42 i43 i43
mpc885/mpc880 hardware specifications, rev. 3 37 freescale semiconductor bus signal timing table 11 shows the pcmcia timing for the mpc885/880. table 11. pcmcia timing num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max p44 a(0:31), reg valid to pcmcia strobe asserted 1 (min = 0.75 b1 ? 2.00) 1 psst = 1. otherwise add psst times cycle time. psht = 0. otherwise add psht times cycle time. these synchronous timings define when the waitx signals are detected in order to freeze (or relieve) the pcmcia current cycle. the waitx assertion will be effective only if it is detected 2 cycles before the psl timer expiration. see chapter 16, ?pcmcia interface,? in the mpc885 powerquicc family user?s manual . 20.70 ? 16.70 ? 9.40 ? 7.40 ? ns p45 a(0:31), reg valid to ale negation 1 (min = 1.00 b1 ? 2.00) 28.30 ? 23.00 ? 13.20 ? 10.50 ? ns p46 clkout to reg valid (max = 0.25 b1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns p47 clkout to reg invalid (min = 0.25 ? b1 + 1.00) 8.60 ? 7.30 ? 4.80 ? 4.13 ? ns p48 clkout to ce1 , ce2 asserted (max = 0.25 b1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns p49 clkout to ce1 , ce2 negated (max = 0.25 b1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns p50 clkout to pcoe , iord , pcwe , iowr assert time (max = 0.00 b1 + 11.00) ? 11.00 ? 11.00 ? 11.00 ? 11.00 ns p51 clkout to pcoe , iord , pcwe , iowr negate time (max = 0.00 b1 + 11.00) 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns p52 clkout to ale assert time (max = 0.25 b1 + 6.30) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns p53 clkout to ale negate time (max = 0.25 b1 + 8.00) ? 15.60 ? 14.30 ? 11.80 ? 11.13 ns p54 pcwe , iowr negated to d(0:31) invalid 1 (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns p55 waita and waitb valid to clkout rising edge 1 (min = 0.00 b1 + 8.00) 8.00 ? 8.00 ? 8.00 ? 8.00 ? ns p56 clkout rising edge to waita and waitb invalid 1 (min = 0.00 b1 + 2.00) 2.00 ? 2.00 ? 2.00 ? 2.00 ? ns
mpc885/mpc880 hardware specifications, rev. 3 38 freescale semiconductor bus signal timing figure 27 provides the pcmcia access cycle timing for the external bus read. figure 27. pcmcia access cycles timing external bus read clkout a[0:31] reg ce1 /ce2 pcoe , iord ts d[0:31] ale b19 b18 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47
mpc885/mpc880 hardware specifications, rev. 3 39 freescale semiconductor bus signal timing figure 28 provides the pcmcia access cycle timing for the external bus write. figure 28. pcmcia access cycles timing external bus write figure 29 provides the pcmcia wait signals detection timing. figure 29. pcmcia wait signals detection timing clkout a[0:31] reg ce1 /ce2 pcwe , iowr ts d[0:31] ale b9 b8 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47 p54 clkout wait x p55 p56
mpc885/mpc880 hardware specifications, rev. 3 40 freescale semiconductor bus signal timing table 12 shows the pcmcia port timing for the mpc885/880. figure 30 provides the pcmcia output port timing for the mpc885/880. figure 30. pcmcia output port timing figure 31 provides the pcmcia input port timing for the mpc885/880. figure 31. pcmcia input port timing table 12. pcmcia port timing num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max p57 clkout to opx valid (max = 0.00 b1 + 19.00) ? 19.00 ? 19.00 ? 19.00 ? 19.00 ns p58 hreset negated to opx drive 1 (min = 0.75 b1 + 3.00) 1 op2 and op3 only. 25.70 ? 21.70 ? 14.40 ? 12.40 ? ns p59 ip_xx valid to clkout rising edge (min = 0.00 b1 + 5.00) 5.00 ? 5.00 ? 5.00 ? 5.00 ? ns p60 clkout rising edge to ip_xx invalid (min = 0.00 b1 + 1.00) 1.00 ? 1.00 ? 1.00 ? 1.00 ? ns clkout hreset output signals op2, op3 p57 p58 clkout input signals p59 p60
mpc885/mpc880 hardware specifications, rev. 3 41 freescale semiconductor bus signal timing table 13 shows the debug port timing for the mpc885/880. figure 32 provides the input timing for the debug port clock. figure 32. debug port clock input timing figure 33 provides the timing for the debug port. figure 33. debug port timings table 13. debug port timing num characteristic all frequencies unit min max d61 dsck cycle time 3 t clocko ut - d62 dsck clock pulse width 1.25 t clo ckout - d63 dsck rise and fall times 0.00 3.00 ns d64 dsdi input data setup time 8.00 ns d65 dsdi data hold time 5.00 ns d66 dsck low to dsdo data valid 0.00 15.00 ns d67 dsck low to dsdo invalid 0.00 2.00 ns dsck d61 d61 d63 d62 d62 d63 dsck dsdi dsdo d64 d65 d66 d67
mpc885/mpc880 hardware specifications, rev. 3 42 freescale semiconductor bus signal timing table 14 shows the reset timing for the mpc885/880. table 14. reset timing num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max r69 clkout to hreset high impedance (max = 0.00 b1 + 20.00) ? 20.00 ? 20.00 ? 20.00 ? 20.00 ns r70 clkout to sreset high impedance (max = 0.00 b1 + 20.00) ? 20.00 ? 20.00 ? 20.00 ? 20.00 ns r71 rstconf pulse width (min = 17.00 b1) 515.20 ? 425.00 ? 257.60 ? 212.50 ? ns r72 ? ????????? r73 configuration data to hreset rising edge setup time (min = 15.00 b1 + 50.00) 504.50 ? 425.00 ? 277.30 ? 237.50 ? ns r74 configuration data to rstconf rising edge setup time (min = 0.00 b1 + 350.00) 350.00 ? 350.00 ? 350.00 ? 350.00 ? ns r75 configuration data hold time after rstconf negation (min = 0.00 b1 + 0.00) 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns r76 configuration data hold time after hreset negation (min = 0.00 b1 + 0.00) 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns r77 hreset and rstconf asserted to data out drive (max = 0.00 b1 + 25.00) ? 25.00 ? 25.00 ? 25.00 ? 25.00 ns r78 rstconf negated to data out high impedance (max = 0.00 b1 + 25.00) ? 25.00 ? 25.00 ? 25.00 ? 25.00 ns r79 clkout of last rising edge before chip three-states hreset to data out high impedance (max = 0.00 b1 + 25.00) ? 25.00 ? 25.00 ? 25.00 ? 25.00 ns r80 dsdi, dsck setup (min = 3.00 b1) 90.90 ? 75.00 ? 45.50 ? 37.50 ? ns r81 dsdi, dsck hold time (min = 0.00 b1 + 0.00) 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns r82 sreset negated to clkout rising edge for dsdi and dsck sample (min = 8.00 b1) 242.40 ? 200.00 ? 121.20 ? 100.00 ? ns
mpc885/mpc880 hardware specifications, rev. 3 43 freescale semiconductor bus signal timing figure 34 shows the reset timing for the data bus configuration. figure 34. reset timing?configuration from data bus figure 35 provides the reset timing for the data bus weak drive during configuration. figure 35. reset timing?data bus weak drive during configuration hreset rstconf d[0:31] (in) r71 r74 r73 r75 r76 clkout hreset d[0:31] (out) (weak) rstconf r69 r79 r77 r78
mpc885/mpc880 hardware specifications, rev. 3 44 freescale semiconductor ieee 1149.1 electrical specifications figure 36 provides the reset timing for the debug port configuration. figure 36. reset timing?debug port configuration 11 ieee 1149.1 electrical specifications table 15 provides the jtag timings for the mpc885/880 shown in figure 37 to figure 40 . table 15. jtag timing num characteristic all frequencies unit min max j82 tck cycle time 100.00 ? ns j83 tck clock pulse width measured at 1.5 v 40.00 ? ns j84 tck rise and fall times 0.00 10.00 ns j85 tms, tdi data setup time 5.00 ? ns j86 tms, tdi data hold time 25.00 ? ns j87 tck low to tdo data valid ? 27.00 ns j88 tck low to tdo data invalid 0.00 ? ns j89 tck low to tdo high impedance ? 20.00 ns j90 trst assert time 100.00 ? ns j91 trst setup time to tck low 40.00 ? ns j92 tck falling edge to output valid ? 50.00 ns j93 tck falling edge to output valid out of high impedance ? 50.00 ns j94 tck falling edge to output high impedance ? 50.00 ns j95 boundary scan input valid to tck rising edge 50.00 ? ns j96 tck rising edge to boundary scan input invalid 50.00 ? ns clkout sreset dsck, dsdi r70 r82 r80 r80 r81 r81
mpc885/mpc880 hardware specifications, rev. 3 45 freescale semiconductor ieee 1149.1 electrical specifications figure 37. jtag test clock input timing figure 38. jtag test access port timing diagram figure 39. jtag trst timing diagram tck j82 j83 j82 j83 j84 j84 tck tms, tdi tdo j85 j86 j87 j88 j89 tck trst j91 j90
mpc885/mpc880 hardware specifications, rev. 3 46 freescale semiconductor cpm electrical characteristics figure 40. boundary scan (jtag) timing diagram 12 cpm electrical characteristics this section provides the ac and dc electrical specifications for the communications processor module (cpm) of the mpc885/880. 12.1 pip/pio ac electrical specifications table 16 provides the pip/pio ac timings as shown in figure 41 to figure 45 . table 16. pip/pio timing num characteristic all frequencies unit min max 21 data-in setup time to stbi low 0 ? ns 22 data-in hold time to stbi high 0 ? clk 23 stbi pulse width 1.5 ? clk 24 stbo pulse width 1 clk ? 5 ns ? ns 25 data-out setup time to stbo low 2 ? clk 26 data-out hold time from stbo high 5 ? clk 27 stbi low to stbo low (rx interlock) ? 4.5 clk 28 stbi low to stbo high (tx interlock) 2 ? clk 29 data-in setup time to clock high 15 ? ns 30 data-in hold time from clock high 7.5 ? ns 31 clock low to data-out valid (cpu writes data, control, or direction) ? 25 ns tck output signals output signals output signals j92 j94 j93 j95 j96
mpc885/mpc880 hardware specifications, rev. 3 47 freescale semiconductor cpm electrical characteristics figure 41. pip rx (interlock mode) timing diagram figure 42. pip tx (interlock mode) timing diagram figure 43. pip rx (pulse mode) timing diagram data-in stbi 23 24 22 stbo 27 21 data-out 24 23 26 28 25 stbo (output) stbi (input) data-in 23 22 21 stbi (input) stbo (output) 24
mpc885/mpc880 hardware specifications, rev. 3 48 freescale semiconductor cpm electrical characteristics figure 44. pip tx (pulse mode) timing diagram figure 45. parallel i/o data-in/data-out timing diagram 12.2 port c interrupt ac electrical specifications table 17 provides the timings for port c interrupts. table 17. port c interrupt timing num characteristic 33.34 mhz unit min max 35 port c interrupt pulse width low (edge-triggered mode) 55 ? ns 36 port c interrupt minimum time between active edges 55 ? ns data-out 24 26 25 stbo (output) stbi (input) 23 clko data-in 29 31 30 data-out
mpc885/mpc880 hardware specifications, rev. 3 49 freescale semiconductor cpm electrical characteristics figure 46 shows the port c interrupt detection timing. figure 46. port c interrupt detection timing 12.3 idma controller ac electrical specifications table 18 provides the idma controller timings as shown in figure 47 to figure 50 . figure 47. idma external requests timing diagram table 18. idma controller timing num characteristic all frequencies unit min max 40 dreq setup time to clock high 7 ? ns 41 dreq hold time from clock high 1 1 applies to high-to-low mode (edm=1) tbd ? ns 42 sdack assertion delay from clock high ? 12 ns 43 sdack negation delay from clock low ? 12 ns 44 sdack negation delay from ta low ? 20 ns 45 sdack negation delay from clock high ? 15 ns 46 ta assertion to falling edge of the clock setup time (applies to external ta )7 ? ns port c 35 36 (input) 41 40 dreq (input) clko (output)
mpc885/mpc880 hardware specifications, rev. 3 50 freescale semiconductor cpm electrical characteristics figure 48. sdack timing diagram?peripheral write, externally-generated ta figure 49. sdack timing diagram?peripheral write, internally-generated ta data 42 46 43 clko (output) ts (output) r/w (output) ta (input) sdack data 42 44 clko (output) ts (output) r/w (output) ta (output) sdack
mpc885/mpc880 hardware specifications, rev. 3 51 freescale semiconductor cpm electrical characteristics figure 50. sdack timing diagram?peripheral read, internally-generated ta 12.4 baud rate generator ac electrical specifications table 19 provides the baud rate generator timings as shown in figure 51 . figure 51. baud rate generator timing diagram table 19. baud rate generator timing num characteristic all frequencies unit min max 50 brgo rise and fall time ? 10 ns 51 brgo duty cycle 40 60 % 52 brgo cycle 40 ? ns data 42 45 clko (output) ts (output) r/w (output) ta (output) sdack 52 50 51 brgox 50 51
mpc885/mpc880 hardware specifications, rev. 3 52 freescale semiconductor cpm electrical characteristics 12.5 timer ac electrical specifications table 20 provides the general-purpose timer timings as shown in figure 52 . figure 52. cpm general-purpose timers timing diagram 12.6 serial interface ac electrical specifications table 21 provides the serial interface timings as shown in figure 53 to figure 57 . table 20. timer timing num characteristic all frequencies unit min max 61 tin/tgate rise and fall time 10 ? ns 62 tin/tgate low time 1 ? clk 63 tin/tgate high time 2 ? clk 64 tin/tgate cycle time 3 ? clk 65 clko low to tout valid 3 25 ns table 21. si timing num characteristic all frequencies unit min max 70 l1rclk, l1tclk frequency (dsc = 0) 1, 2 ? syncclk /2.5 mhz 71 l1rclk, l1tclk width low (dsc = 0) 2 p + 10 ? ns 71a l1rclk, l1tclk width high (dsc = 0) 3 p + 10 ? ns 72 l1txd, l1st(1?4), l1rq , l1clko rise/fall time ? 15.00 ns 73 l1rsync, l1tsync valid to l1clk edge (sync setup time) 20.00 ? ns 74 l1clk edge to l1rsync, l1tsync, invalid (sync hold time) 35.00 ? ns clko tin/tgate (input) tout (output) 64 65 61 62 63 61 60
mpc885/mpc880 hardware specifications, rev. 3 53 freescale semiconductor cpm electrical characteristics 75 l1rsync, l1tsync rise/fall time ? 15.00 ns 76 l1rxd valid to l1clk edge (l1rxd setup time) 17.00 ? ns 77 l1clk edge to l1rxd invalid (l1rxd hold time) 13.00 ? ns 78 l1clk edge to l1st(1?4) valid 4 10.00 45.00 ns 78a l1sync valid to l1st(1?4) valid 10.00 45.00 ns 79 l1clk edge to l1st(1?4) invalid 10.00 45.00 ns 80 l1clk edge to l1txd valid 10.00 55.00 ns 80a l1tsync valid to l1txd valid 4 10.00 55.00 ns 81 l1clk edge to l1txd high impedance 0.00 42.00 ns 82 l1rclk, l1tclk frequency (dsc =1) ? 16.00 or syncclk /2 mhz 83 l1rclk, l1tclk width low (dsc =1) p + 10 ? ns 83a l1rclk, l1tclk width high (dsc = 1) 3 p + 10 ? ns 84 l1clk edge to l1clko valid (dsc = 1) ? 30.00 ns 85 l1rq valid before falling edge of l1tsync 4 1.00 ? l1tclk 86 l1gr setup time 2 42.00 ? ns 87 l1gr hold time 42.00 ? ns 88 l1clk edge to l1sync valid (fsd = 00) cnt = 0000, byt = 0, dsc = 0) ?0.00ns 1 the ratio syncclk/l1rclk must be greater than 2.5/1. 2 these specs are valid for idl mode only. 3 where p = 1/clkout. thus for a 25-mhz clko1 rate, p = 40 ns. 4 these strobes and txd on the first bit of the frame become valid after l1clk edge or l1sync, whichever comes later. table 21. si timing (continued) num characteristic all frequencies unit min max
mpc885/mpc880 hardware specifications, rev. 3 54 freescale semiconductor cpm electrical characteristics figure 53. si receive timing diagram with normal clocking (dsc = 0) l1rxd (input) l1rclk ( fe=0, ce=0) (input) l1rclk ( fe=1, ce=1) (input) l1rsync (input) l1st(4-1) (output) 71 72 70 71a rfsd=1 75 73 74 77 78 76 79 bit0
mpc885/mpc880 hardware specifications, rev. 3 55 freescale semiconductor cpm electrical characteristics figure 54. si receive timing with double-speed clocking (dsc = 1) l1rxd (input) l1rclk ( fe=1, ce=1) (input) l1rclk ( fe=0, ce=0) (input) l1rsync (input) l1st(4-1) (output) 72 rfsd=1 75 73 74 77 78 76 79 83a 82 l1clko (output) 84 bit0
mpc885/mpc880 hardware specifications, rev. 3 56 freescale semiconductor cpm electrical characteristics figure 55. si transmit timing diagram (dsc = 0) l1txd (output) l1tclk ( fe=0, ce=0) (input) l1tclk ( fe=1, ce=1) (input) l1tsync (input) l1st(4-1) (output) 71 70 72 73 75 74 80a 80 78 tfsd=0 81 79 bit0
mpc885/mpc880 hardware specifications, rev. 3 57 freescale semiconductor cpm electrical characteristics figure 56. si transmit timing with double speed clocking (dsc = 1) l1txd (output) l1rclk ( fe=0, ce=0) (input) l1rclk ( fe=1, ce=1) (input) l1rsync (input) l1st(4-1) (output) 72 tfsd=0 75 73 74 78a 80 79 83a 82 l1clko (output) 84 bit0 78 81
mpc885/mpc880 hardware specifications, rev. 3 58 freescale semiconductor cpm electrical characteristics figure 57. idl timing b17 b16 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m b15 l1rxd (input) l1txd (output) l1st(4-1) (output) l1rq (output) 73 77 123456789 10 11 12 13 14 15 16 17 18 19 20 74 80 b17 b16 b15 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m 71 71 l1gr (input) 78 85 72 76 87 86 l1rsync (input) l1rclk (input) 81
mpc885/mpc880 hardware specifications, rev. 3 59 freescale semiconductor cpm electrical characteristics 12.7 scc in nmsi mode electrical specifications table 22 provides the nmsi external clock timing. table 23 provides the nmsi internal clock timing. table 22. nmsi external clock timing num characteristic all frequencies unit min max 100 rclk1 and tclk1 width high 1 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater than or equal to 2.25/1. 1/syncclk ? ns 101 rclk1 and tclk1 width low 1/syncclk + 5 ? ns 102 rclk1 and tclk1 rise/fall time ? 15.00 ns 103 txd1 active delay (from tclk1 falling edge) 0.00 50.00 ns 104 rts1 active/inactive delay (from tclk1 falling edge) 0.00 50.00 ns 105 cts1 setup time to tclk1 rising edge 5.00 ? ns 106 rxd1 setup time to rclk1 rising edge 5.00 ? ns 107 rxd1 hold time from rclk1 rising edge 2 2 also applies to cd and cts hold time when they are used as external sync signals. 5.00 ? ns 108 cd1 setup time to rclk1 rising edge 5.00 ? ns table 23. nmsi internal clock timing num characteristic all frequencies unit min max 100 rclk1 and tclk1 frequency 1 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater than or equal to 3/1. 0.00 syncclk/3 mhz 102 rclk1 and tclk1 rise/fall time ? ? ns 103 txd1 active delay (from tclk1 falling edge) 0.00 30.00 ns 104 rts1 active/inactive delay (from tclk1 falling edge) 0.00 30.00 ns 105 cts1 setup time to tclk1 rising edge 40.00 ? ns 106 rxd1 setup time to rclk1 rising edge 40.00 ? ns 107 rxd1 hold time from rclk1 rising edge 2 2 also applies to cd and cts hold time when they are used as external sync signals 0.00 ? ns 108 cd1 setup time to rclk1 rising edge 40.00 ? ns
mpc885/mpc880 hardware specifications, rev. 3 60 freescale semiconductor cpm electrical characteristics figure 58 through figure 60 show the nmsi timings. figure 58. scc nmsi receive timing diagram figure 59. scc nmsi transmit timing diagram rclk1 cd1 (input) 102 100 107 108 107 rxd1 (input) cd1 (sync input) 102 101 106 tclk1 cts1 (input) 102 100 104 107 txd1 (output) cts1 (sync input) 102 101 rts1 (output) 105 103 104
mpc885/mpc880 hardware specifications, rev. 3 61 freescale semiconductor cpm electrical characteristics figure 60. hdlc bus timing diagram 12.8 ethernet electrical specifications table 24 provides the ethernet timings as shown in figure 61 to figure 63 . table 24. ethernet timing num characteristic all frequencies unit min max 120 clsn width high 40 ? ns 121 rclk1 rise/fall time ? 15 ns 122 rclk1 width low 40 ? ns 123 rclk1 clock period 1 80 120 ns 124 rxd1 setup time 20 ? ns 125 rxd1 hold time 5 ? ns 126 rena active delay (from rclk1 rising edge of the last data bit) 10 ? ns 127 rena width low 100 ? ns 128 tclk1 rise/fall time ? 15 ns 129 tclk1 width low 40 ? ns 130 tclk1 clock period 1 99 101 ns 131 txd1 active delay (from tclk1 rising edge) ? 50 ns 132 txd1 inactive delay (from tclk1 rising edge) 6.5 50 ns 133 tena active delay (from tclk1 rising edge) 10 50 ns tclk1 cts1 (echo input) 102 100 104 txd1 (output) 102 101 rts1 (output) 103 104 107 105
mpc885/mpc880 hardware specifications, rev. 3 62 freescale semiconductor cpm electrical characteristics figure 61. ethernet collision timing diagram figure 62. ethernet receive timing diagram 134 tena inactive delay (from tclk1 rising edge) 10 50 ns 138 clko1 low to sdack asserted 2 ?20ns 139 clko1 low to sdack negated 2 ?20ns 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater than or equal to 2/1. 2 sdack is asserted whenever the sdma writes the incoming frame da into memory. table 24. ethernet timing (continued) num characteristic all frequencies unit min max clsn(cts1 ) 120 (input) rclk1 121 rxd1 (input) 121 rena(cd1 ) (input) 125 124 123 127 126 last bit
mpc885/mpc880 hardware specifications, rev. 3 63 freescale semiconductor cpm electrical characteristics figure 63. ethernet transmit timing diagram 12.9 smc transparent ac electrical specifications table 25 provides the smc transparent timings as shown in figure 64 . table 25. smc transparent timing num characteristic all frequencies unit min max 150 smclk clock period 1 1 syncclk must be at least twice as fast as smclk. 100 ? ns 151 smclk width low 50 ? ns 151a smclk width high 50 ? ns 152 smclk rise/fall time ? 15 ns 153 smtxd active delay (from smclk falling edge) 10 50 ns 154 smrxd/smsync setup time 20 ? ns 155 rxd1/smsync hold time 5 ? ns tclk1 128 txd1 (output) 128 tena(rts1 ) (input) notes: transmit clock invert (tci) bit in gsmr is set. if rena is negated before tena or rena is not asserted at all during transmit, then the csl bit is set in the buffer descriptor at the end of the frame transmission. 1. 2. rena(cd1 ) (input) 133 134 132 131 121 129 (note 2)
mpc885/mpc880 hardware specifications, rev. 3 64 freescale semiconductor cpm electrical characteristics figure 64. smc transparent timing diagram 12.10spi master ac electrical specifications table 26 provides the spi master timings as shown in figure 65 and figure 66 . table 26. spi master timing num characteristic all frequencies unit min max 160 master cycle time 4 1024 t cyc 161 master clock (sck) high or low time 2 512 t cyc 162 master data setup time (inputs) 15 ? ns 163 master data hold time (inputs) 0 ? ns 164 master data valid (after sck edge) ? 10 ns 165 master data hold time (outputs) 0 ? ns 166 rise time output ? 15 ns 167 fall time output ? 15 ns smclk smrxd (input) 152 150 smtxd (output) 152 151 smsync 151 154 153 155 154 155 note note: this delay is equal to an integer number of character-length clocks. 1.
mpc885/mpc880 hardware specifications, rev. 3 65 freescale semiconductor cpm electrical characteristics figure 65. spi master (cp = 0) timing diagram figure 66. spi master (cp = 1) timing diagram spimosi (output) spiclk (ci=0) (output) spiclk (ci=1) (output) spimiso (input) 162 data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 spimosi (output) spiclk (ci=0) (output) spiclk (ci=1) (output) spimiso (input) data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 162
mpc885/mpc880 hardware specifications, rev. 3 66 freescale semiconductor cpm electrical characteristics 12.11spi slave ac electrical specifications table 27 provides the spi slave timings as shown in figure 67 and figure 68 . figure 67. spi slave (cp = 0) timing diagram table 27. spi slave timing num characteristic all frequencies unit min max 170 slave cycle time 2 ? t cyc 171 slave enable lead time 15 ? ns 172 slave enable lag time 15 ? ns 173 slave clock (spiclk) high or low time 1 ? t cyc 174 slave sequential transfer delay (does not require deselect) 1 ? t cyc 175 slave data setup time (inputs) 20 ? ns 176 slave data hold time (inputs) 20 ? ns 177 slave access time ? 50 ns spimosi (input) spiclk (ci=0) (input) spiclk (ci=1) (input) spimiso (output) 180 data 181 182 173 173 170 msb lsb msb 181 177 182 175 179 spisel (input) 171 172 174 data msb lsb msb undef 181 178 176 182
mpc885/mpc880 hardware specifications, rev. 3 67 freescale semiconductor cpm electrical characteristics figure 68. spi slave (cp = 1) timing diagram 12.12i 2 c ac electrical specifications table 28 provides the i 2 c (scl < 100 khz) timings. table 28. i 2 c timing (scl < 100 kh z ) num characteristic all frequencies unit min max 200 scl clock frequency (slave) 0 100 khz 200 scl clock frequency (master) 1 1.5 100 khz 202 bus free time between transmissions 4.7 ? s 203 low period of scl 4.7 ? s 204 high period of scl 4.0 ? s 205 start condition setup time 4.7 ? s 206 start condition hold time 4.0 ? s 207 data hold time 0 ? s 208 data setup time 250 ? ns 209 sdl/scl rise time ? 1 s spimosi (input) spiclk (ci=0) (input) spiclk (ci=1) (input) spimiso (output) 180 data 181 182 msb lsb 181 177 182 175 179 spisel (input) 174 data msb lsb undef 178 176 182 msb msb 172 173 173 171 170 181
mpc885/mpc880 hardware specifications, rev. 3 68 freescale semiconductor cpm electrical characteristics table 29 provides the i 2 c (scl > 100 khz) timings. 210 sdl/scl fall time ? 300 ns 211 stop condition setup time 4.7 ? s 1 scl frequency is given by scl = brgclk_frequency / ((brg register + 3) pre_scaler 2). the ratio syncclk/(brgclk/pre_scaler) must be greater or equal to 4/1. table 29. i 2 c timing (scl > 100 kh z ) num characteristic expression all frequencies unit min max 200 scl clock frequency (slave) fscl 0 brgclk/48 hz 200 scl clock frequency (master) 1 1 scl frequency is given by scl = brgclk_frequency / ((brg register + 3) pre_scaler 2). the ratio syncclk/(brg_clk/pre_scaler) must be greater or equal to 4/1. fscl brgclk/16512 brgclk/48 hz 202 bus free time between transmissions ? 1/(2.2 fscl) ? s 203 low period of scl ? 1/(2.2 fscl) ? s 204 high period of scl ? 1/(2.2 fscl) ? s 205 start condition setup time ? 1/(2.2 fscl) ? s 206 start condition hold time ? 1/(2.2 fscl) ? s 207 data hold time ? 0 ? s 208 data setup time ? 1/(40 fscl) ? s 209 sdl/scl rise time ? ? 1/(10 fscl) s 210 sdl/scl fall time ? ? 1/(33 fscl) s 211 stop condition setup time ? 1/2(2.2 fscl) ? s table 28. i 2 c timing (scl < 100 kh z ) (continued) num characteristic all frequencies unit min max
mpc885/mpc880 hardware specifications, rev. 3 69 freescale semiconductor utopia ac electrical specifications figure 69 shows the i 2 c bus timing. figure 69. i 2 c bus timing diagram 13 utopia ac electrical specifications table 30 , table 31 , and table 32 , show the ac electrical specifications for the utopia interface. table 30. utopia master (muxed mode) electrical specifications num signal characteristic direction min max unit u1 utpclk rise/fall time (internal clock option) output 4 ns ns duty cycle 50 50 % frequency 33 mhz u2 utpb, soc, rxenb , txenb , rxaddr, and txaddr active delay (and phreq and phsel active delay in multi-phy mode) output 2 ns 16 ns ns u3 utpb, soc, rxclav and txclav setup time input 4 ns ns u4 utpb, soc, rxclav and txclav hold time input 1 ns ns table 31. utopia master (split bus mode) electrical specifications num signal characteristic direction min max unit u1 utpclk rise/fall time (internal clock option) output 4 ns ns duty cycle 50 50 % frequency 33 mhz u2 utpb, soc, rxenb , txenb, rxaddr and txaddr active delay (phreq and phsel active delay in multi-phy mode) output 2 ns 16 ns ns u3 utpb_aux, soc_aux, rxclav and txclav setup time input 4 ns ns u4 utpb_aux, soc_aux, rxclav and txclav hold time input 1 ns ns scl 202 205 203 207 204 208 206 209 211 210 sda
mpc885/mpc880 hardware specifications, rev. 3 70 freescale semiconductor utopia ac electrical specifications figure 70 shows signal timings during utopia receive operations. figure 70. utopia receive timing table 32. utopia slave (split bus mode) electrical specifications num signal characteristic direction min max unit u1 utpclk rise/fall time (external clock option) input 4 ns ns duty cycle 40 60 % frequency 33 mhz u2 utpb, soc, rxclav and txclav active delay output 2 ns 16 ns ns u3 utpb_aux, soc_aux, rxenb , txenb , rxaddr, and txaddr setup time input 4 ns ns u4 utpb_aux, soc_aux, rxenb , txenb , rxaddr, and txaddr hold time input 1 ns ns utpclk utpb rxenb u1 3 2 soc 4 rxclav phreqn 3 4 high-z at mphy high-z at mphy u1 u2 u3 u4 u4 u3 u2
mpc885/mpc880 hardware specifications, rev. 3 71 freescale semiconductor usb electrical characteristics figure 71 shows signal timings during utopia transmit operations. figure 71. utopia transmit timing 14 usb electrical characteristics this section provides the ac timings for the usb interface. 14.1 usb interface ac timing specifications the usb port uses the transmit clock on scc1. table 33 lists the usb interface timings. 15 fec electrical characteristics this section provides the ac electrical specifications for the fast ethernet controller (fec). note that the timing specifications for the mii signals are independent of system clock frequency (part speed designation). also, mii signals use ttl signal levels compatible with devices operating at either 5.0 v or 3.3 v. table 33. usb interface ac timing specifications name characteristic all frequencies unit min max us1 usbclk frequency of operation 1 low speed full speed 1 usbclk accuracy should be 500 ppm or better. usbclk may be stopped to conserve power. 6 48 mhz mhz us4 usbclk duty cycle (measured at 1.5 v) 45 55 % utpclk utpb txenb 1 2 soc 5 txclav phseln 3 4 5 high-z at mphy high-z at multi-ph yp u1 u1 u2 u2 u2 u3 u4
mpc885/mpc880 hardware specifications, rev. 3 72 freescale semiconductor fec electrical characteristics 15.1 mii and reduced mii receive signal timing the receiver functions correctly up to a mii_rx_clk maximum frequency of 25 mhz + 1%. the reduced mii (rmii) receiver functions correctly up to a rmii_refclk maximum frequency of 50 mhz + 1%. there is no minimum frequency requirement. in addition, the processor clock frequency must exceed the mii_rx_clk frequency ? 1%. table 34 provides information on the mii and rmii receive signal timing. figure 72 shows mii receive signal timing. figure 72. mii receive signal timing diagram 15.2 mii and reduced mii transmit signal timing the transmitter functions correctly up to a mii_tx_clk maximum frequency of 25 mhz +1%. the rmii transmitter functions correctly up to a rmii_refclk maximum frequency of 50 mhz +1%. there is no minimum frequency requirement. in addition, the processor clock frequency must exceed the mii_tx_clk frequency ? 1%. table 34. mii receive signal timing num characteristic min max unit m1 mii_rxd[3:0], mii_rx_dv, mii_rx_err to mii_rx_clk setup 5 ? ns m2 mii_rx_clk to mii_rxd[3:0], mii_rx_dv, mii_rx_er hold 5 ? ns m3 mii_rx_clk pulse width high 35% 65% mii_rx_clk period m4 mii_rx_clk pulse width low 35% 65% mii_rx_clk period m1_rmii rmii_rxd[1:0], rmii_crs_dv, rmii_rx_err to rmii_refclk setup 4? ns m2_rmii rmii_refclk to rmii_rxd[1:0], rmii_crs_dv, rmii_rx_err hold 2? ns m1 m2 mii_rx_clk (input) mii_rxd[3:0] (inputs) mii_rx_dv mii_rx_er m3 m4
mpc885/mpc880 hardware specifications, rev. 3 73 freescale semiconductor fec electrical characteristics table 35 provides information on the mii and rmii transmit signal timing. figure 73 shows the mii transmit signal timing diagram. figure 73. mii transmit signal timing diagram 15.3 mii async inputs signal timing (mii_crs, mii_col) table 36 provides information on the mii async inputs signal timing. table 35. mii transmit signal timing num characteristic min max unit m5 mii_tx_clk to mii_txd[3:0], mii_tx_en, mii_tx_er invalid 5 ? ns m6 mii_tx_clk to mii_txd[3:0], mii_tx_en, mii_tx_er valid ? 25 ns m20_r mii rmii_txd[1:0], rmii_tx_en to rmii_refclk setup 4 ? ns m21_r mii rmii_txd[1:0], rmii_tx_en data hold from rmii_refclk rising edge 2? ns m7 mii_tx_clk and rmii_refclk pulse width high 35% 65% mii_tx_clk or rmii_refclk period m8 mii_tx_clk and rmii_refclk pulse width low 35% 65% mii_tx_clk or rmii_refclk period table 36. mii async inputs signal timing num characteristic min max unit m9 mii_crs, mii_col minimum pulse width 1.5 ? mii_tx_clk period m6 mii_tx_clk (input) mii_txd[3:0] (outputs) mii_tx_en mii_tx_er m5 m7 m8 rmii_refclk
mpc885/mpc880 hardware specifications, rev. 3 74 freescale semiconductor fec electrical characteristics figure 74 shows the mii asynchronous inputs signal timing diagram. figure 74. mii async inputs timing diagram 15.4 mii serial management channel timing (mii_mdio, mii_mdc) table 37 provides information on the mii serial management channel signal timing. the fec functions correctly with a maximum mdc frequency in excess of 2.5 mhz. the exact upper bound is under investigation. figure 75 shows the mii serial management channel timing diagram. figure 75. mii serial management channel timing diagram table 37. mii serial management channel timing num characteristic min max unit m10 mii_mdc falling edge to mii_mdio output invalid (minimum propagation delay) 0? ns m11 mii_mdc falling edge to mii_mdio output valid (max prop delay) ? 25 ns m12 mii_mdio (input) to mii_mdc rising edge setup 10 ? ns m13 mii_mdio (input) to mii_mdc rising edge hold 0 ? ns m14 mii_mdc pulse width high 40% 60% mii_mdc period m15 mii_mdc pulse width low 40% 60% mii_mdc period mii_crs, mii_col m9 m11 mii_mdc (output) mii_mdio (output) m12 m13 mii_mdio (input) m10 m14 mm15
mpc885/mpc880 hardware specifications, rev. 3 75 freescale semiconductor mechanical data and ordering information 16 mechanical data and ordering information table 38 identifies the available packages and operating frequencies for the mpc885/880 derivative devices. table 38. available mpc885/880 packages/frequencies package type temperature (tj) frequency (mhz) order number plastic ball grid array zp suffix ? leaded vr suffix ? lead-free are available as needed 0c to 95c 66 kmpc885zp66 KMPC880zp66 mpc885zp66 mpc880zp66 80 kmpc885zp80 KMPC880zp80 mpc885zp80 mpc880zp80 133 kmpc885zp133 KMPC880zp133 mpc885zp133 mpc880zp133 plastic ball grid array czp suffix ? leaded cvr suffix ? lead-free are available as needed -40c to 100c 66 kmpc885czp66 KMPC880czp66 mpc885czp66 mpc880czp66 133 kmpc885czp133 KMPC880czp133 mpc885czp133 mpc880czp133
mpc885/mpc880 hardware specifications, rev. 3 76 freescale semiconductor mechanical data and ordering information 16.1 pin assignments figure 76 shows the top-view pinout of the pbga package. for additional information, see the mpc885 powerquicc family user?s manual . note: this is the top view of the device. figure 76. pinout of the pbga package pb23 pa8 pc8 pa5 pb17 pa13 pc4 pa11 pe17 pe30 pe15 pd6 pd7 pa3 pd4 oe cs5 gpl_b4 bdip ts irq3 ipb5 ipb0 ipb6 baddr30 modck2 extclk sreset wait_a xtal gpl_ab3 cs2 18 16 14 13 12 11 10 9 8 7 6 5 3 2 4 17 15 1 19 we0 cs7 cs0 gpl_a4 tea bb irq2 ipb4 ipb7 alea op0 baddr29 poreset vddlsyn hreset gpl_a0 ce1_a i pa0 we3 bsa1 cs4 cs1 gpl_a5 ta bg burst ipb3 ipb2 irq4 op1 baddr28 wait_b vsssyn1 texp we2 ce2_a ipa1 bsa2 a31 gpl_ab2 cs3 wr bi br irq6 ipb1 aleb as modck1 extal ipa7 ipa4 rstconf bsa0 cs6 ipa5 a26 a28 we1 ipa3 ipa6 vsssyn tsiz1 d30 a18 a30 bsa3 d31 d7 ipa2 a22 d29 a25 a29 tsiz0 d26 d24 clkout a23 d25 a21 a19 a24 d6 d20 d28 a20 d21 a27 a16 a17 d19 d16 d22 a15 d18 a14 a11 a13 d14 d3 d5 a12 d15 a10 a9 a6 d10 d11 d9 a8 d2 a7 a5 a0 d23 d27 d17 a4 d1 a3 a1 pa15 d12 d13 irq0 n/c d4 a2 pb30 pa12 irq1 irq7 pa14 d8 mii_mdio pc14 pd8 pe20 pb26 pe18 pc15 pc12 tdi pc9 pb20 pb18 mii1_crs pc5 pd3 pe29 pe16 pe19 mii1_txen pe25 pd10 pa2 tdo pa9 pe26 pb29 pb14 pb24 pb21 pa6 mii1_col pc6 pb15 pe31 pd15 pd14 pd13 pd12 pa0 pd9 pa4 tck pc10 pa1 pb27 tms pc11 pa7 pb19 pc7 pb16 pc13 pe21 pe24 pe14 pd5 pe28 pb31 pe23 pe27 pb25 pb22 pe22 pb28 b a c d e f g h j k l m n p r t u v w trst pa10 vddl vddl vddl vddl pd11 d0 vddl vddl vddl vddl vddl vddl vddl vddl vddl vddl vddh vddh vddh vddh vddh vddh vddh vddh vddh vddh vddh gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd
mpc885/mpc880 hardware specifications, rev. 3 77 freescale semiconductor mechanical data and ordering information table 39 contains a list of the mpc885 input and output signals and shows multiplexing and pin assignments. table 39. pin assignments name pin number type a[0:31] m16, n18, n19, m19, m17, m18, l16, l19, l17, l18, k19, k18, k17, k16, j19, j17, j18, j16, e19, h18, h17, g19, f17, g17, h16, f19, d19, h19, e18, g18, f18, d18 bidirectional three-state d[0:31] p2, m1, l1, k2, n1, k4, h3, f2, p1, l4, l3, l2, n3, n2, k3, k1, j2, m4, j1, j3, h2, h1, j4, m3, g2, g1, g3, m2, h4, f1, e1, f3 bidirectional three-state tsiz0 reg g16 bidirectional three-state tsiz1 e17 bidirectional three-state rd/wr d13 bidirectional three-state burst c10 bidirectional three-state bdip gpl_b5 a13 output ts a12 bidirectional active pull-up ta c12 bidirectional active pull-up tea b12 open-drain bi d12 bidirectional active pull-up irq2 rsv b10 bidirectional three-state irq4 kr retry spkrout c7 bidirectional three-state cr irq3 a11 input br d11 bidirectional bg c11 bidirectional bb b11 bidirectional active pull-up frz irq6 d10 bidirectional irq0 n4 input irq1 p3 input irq7 p4 input
mpc885/mpc880 hardware specifications, rev. 3 78 freescale semiconductor mechanical data and ordering information cs [0:5] b14, c14, a15, d14, c16, a16 output cs6 ce1_b d15 output cs7 ce2_b b16 output we0 bs_b0 iord b18 output we1 bs_b1 iowr e16 output we2 bs_b2 pcoe c17 output we3 bs_b3 pcwe b19 output bs_a [0:3] d17, c18, c19, f16 output gpl_a0 gpl_b0 b17 output oe gpl_a1 gpl_b1 a18 output gpl_a [2:3] gpl_b [2:3] cs [2:3] d16, a17 output upwaita gpl_a4 b13 bidirectional upwaitb gpl_b4 a14 bidirectional gpl_a5 c13 output poreset b3 input rstconf d4 input hreset b4 open-drain sreset a3 open-drain xtal a4 analog output extal d5 analog input (3.3 v only) clkout g4 output extclk a5 input (3.3 v only) table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 79 freescale semiconductor mechanical data and ordering information texp c4 output ale_a b7 output ce1_a b15 output ce2_a c15 output wait_a soc_split 1 a2 input wait_b c3 input ip_a0 utpb_split0 1 b1 input ip_a1 utpb_split1 1 c1 input ip_a2 iois16_a utpb_split2 1 f4 input ip_a3 utpb_split3 1 e3 input ip_a4 utpb_split4 1 d2 input ip_a5 utpb_split5 1 d1 input ip_a6 utpb_split6 1 e2 input ip_a7 utpb_split7 1 d3 input ale_b dsck/at1 d8 bidirectional three-state ip_b[0:1] iwp[0:1] vfls[0:1] a9, d9 bidirectional ip_b2 iois16_b at2 c8 bidirectional three-state ip_b3 iwp2 vf2 c9 bidirectional ip_b4 lwp0 vf0 b9 bidirectional ip_b5 lwp1 vf1 a10 bidirectional table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 80 freescale semiconductor mechanical data and ordering information ip_b6 dsdi at0 a8 bidirectional three-state ip_b7 ptr at3 b8 bidirectional three-state op0 utpclk_split 1 b6 bidirectional op1 c6 output op2 modck1 sts d6 bidirectional op3 modck2 dsdo a6 bidirectional baddr30 reg a7 output baddr[28:29] c5, b5 output as d7 input pa15 usbrxd n16 bidirectional pa14 usboe p17 bidirectional (optional: open-drain) pa13 rxd2 w11 bidirectional pa12 txd2 p16 bidirectional (optional: open-drain) pa11 rxd4 mii1-txd0 rmii1-txd0 w9 bidirectional (optional: open-drain) pa10 mii1-txer tin4 clk7 w17 bidirectional (optional: open-drain) pa9 l1txda rxd3 t15 bidirectional (optional: open-drain) pa8 l1rxda txd3 w15 bidirectional (optional: open-drain) table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 81 freescale semiconductor mechanical data and ordering information pa7 clk1 l1rclka brgo1 tin1 v14 bidirectional pa6 clk2 tout1 u13 bidirectional pa5 clk3 l1tclka brgo2 tin2 w13 bidirectional pa4 cts4 mii1-txd1 rmii1-txd1 u4 bidirectional pa3 mii1-rxer rmii1-rxer brgo3 w2 bidirectional pa2 mii1-rxdv rmii1-crs_dv txd4 t4 bidirectional pa1 mii1-rxd0 rmii1-rxd0 brgo4 u1 bidirectional pa0 mii1-rxd1 rmii1-rxd1 tout4 u3 bidirectional pb31 spisel mii1 - txclk rmii1-refclk v3 bidirectional (optional: open-drain) pb30 spiclk p18 bidirectional (optional: open-drain) pb29 spimosi t19 bidirectional (optional: open-drain) pb28 spimiso brgo4 v19 bidirectional (optional: open-drain) table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 82 freescale semiconductor mechanical data and ordering information pb27 i2csda brgo1 u19 bidirectional (optional: open-drain) pb26 i2cscl brgo2 r17 bidirectional (optional: open-drain) pb25 rxaddr3 1 txaddr3 smtxd1 v17 bidirectional (optional: open-drain) pb24 txaddr3 1 rxaddr3 smrxd1 u16 bidirectional (optional: open-drain) pb23 txaddr2 1 rxaddr2 sdack1 smsyn1 w16 bidirectional (optional: open-drain) pb22 txaddr4 1 rxaddr4 sdack2 smsyn2 v15 bidirectional (optional: open-drain) pb21 smtxd2 txaddr1 1 brg01 rxaddr1 phsel[1] u14 bidirectional (optional: open-drain) pb20 smrxd2 l1clkoa txaddr0 1 rxaddr0 phsel[0] t13 bidirectional (optional: open-drain) pb19 mii1-rxd3 rts4 v13 bidirectional (optional: open-drain) pb18 rxaddr4 1 txaddr4 rts2 l1st2 t12 bidirectional (optional: open-drain) table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 83 freescale semiconductor mechanical data and ordering information pb17 l1st3 brgo2 rxaddr1 1 txaddr1 phreq[1] w12 bidirectional (optional: open-drain) pb16 l1rqa l1st4 rts4 rxaddr0 1 txaddr0 phreq[0] v11 bidirectional (optional: open-drain) pb15 txclav brg03 rxclav u10 bidirectional pb14 rxaddr2 1 txaddr2 u18 bidirectional pc15 dreq0 rts3 l1st1 txclav rxclav r19 bidirectional pc14 dreq1 rts2 l1st2 r18 bidirectional pc13 mii1-txd3 sdack1 v10 bidirectional pc12 mii1-txd2 tout1 t18 bidirectional pc11 usbrxp v16 bidirectional pc10 usbrxn tgate1 u15 bidirectional pc9 cts2 t14 bidirectional pc8 cd2 tgate2 w14 bidirectional table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 84 freescale semiconductor mechanical data and ordering information pc7 cts4 l1tsyncb usbtxp v12 bidirectional pc6 cd4 l1rsyncb usbtxn u11 bidirectional pc5 cts3 l1tsynca sdack2 t10 bidirectional pc4 cd3 l1rsynca w10 bidirectional pd15 l1tsynca utpb0 u8 bidirectional pd14 l1rsynca utpb1 u7 bidirectional pd13 l1tsyncb utpb2 u6 bidirectional pd12 l1rsyncb utpb3 u5 bidirectional pd11 rxd3 rxenb r2 bidirectional pd10 txd3 txenb t2 bidirectional pd9 txd4 utpclk u2 bidirectional pd8 rxd4 mii-mdc rmii-mdc r3 bidirectional pd7 rts3 utpb4 w3 bidirectional table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 85 freescale semiconductor mechanical data and ordering information pd6 rts4 utpb5 w5 bidirectional pd5 clk8 l1tclkb utpb6 v6 bidirectional pd4 clk4 utpb7 w4 bidirectional pd3 clk7 tin4 soc t9 bidirectional pe31 clk8 l1tclkb mii1-rxclk u9 bidirectional (optional: open-drain) pe30 l1rxdb mii1-rxd2 w7 bidirectional (optional: open-drain) pe29 mii2-crs t8 bidirectional (optional: open-drain) pe28 tout3 mii2-col v5 bidirectional (optional: open-drain) pe27 rts3 l1rqb mii2-rxer rmii2-rxer v4 bidirectional (optional: open-drain) pe26 l1clkob mii2-rxdv rmii2-crs_dv t1 bidirectional (optional: open-drain) pe25 rxd4 mii2-rxd3 l1st2 t3 bidirectional (optional: open-drain) pe24 smrxd1 brgo1 mii2-rxd2 v8 bidirectional (optional: open-drain) table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 86 freescale semiconductor mechanical data and ordering information pe23 smsyn2 txd4 mii2-rxclk l1st1 v2 bidirectional (optional: open-drain) pe22 tout2 mii2-rxd1 rmii2-rxd1 sdack1 v1 bidirectional (optional: open-drain) pe21 smrxd2 tout1 mii2-rxd0 rmii2-rxd0 rts3 v9 bidirectional (optional: open-drain) pe20 l1rsynca smtxd2 cts3 mii2-txer r4 bidirectional (optional: open-drain) pe19 l1txdb mii2-txen rmii2-txen t6 bidirectional (optional: open-drain) pe18 l1tsynca smtxd1 mii2-txd3 r1 bidirectional (optional: open-drain) pe17 tin3 clk5 brgo3 smsyn1 mii2-txd2 w8 bidirectional (optional: open-drain) pe16 l1rclkb clk6 txd3 mii2-txclk rmii2-refclk t7 bidirectional (optional: open-drain) pe15 tgate1 mii2-txd1 rmii2-txd1 w6 bidirectional table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 87 freescale semiconductor mechanical data and ordering information pe14 rxd3 mii2-txd0 rmii2-txd0 v7 bidirectional tms v18 input tdi dsdi t16 input tck dsck u17 input trst w18 input tdo dsdo t17 output mii1_crs t11 input mii_mdio p19 bidirectional mii1_txen rmii1_txen t5 output mii1_col u12 input v sssyn1 c2 pll analog v dd and gnd v sssyn e4 power v ddlsyn b2 power gnd g6, g7, g8, g9, g10, g11, g12, g13, h7, h8, h9, h10, h11, h12, h13, h14, j7, j8, j9, j10, j11, j12, j13, k7, k8, k9, k10, k11, k12, k13, l7, l8, l9, l10, l11, l12, l13, m7, m8, m9, m10, m11, m12, m13, n7, n8, n9, n10, n11, n12, n13, n14, p7, p13, r16 power v ddl e5, e6, e9, e11, e14, g15, h5, j5, j15, k15, l5, m15, n5, r6, r9, r10, r12, r15 power v ddh e7, e8, e10, e12, e13, e15, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, g5, g14, h6, h15, j6, j14, k5, k6, k14, l6, l14, l15, m5, m6, m14, n6, n15, p5, p6, p8, p9, p10, p11, p12, p14, p15, r5, r7, r8, r11, r13, r14 power n/c n17 no-connect 1 esar mode only. table 39. pin assignments (continued) name pin number type
mpc885/mpc880 hardware specifications, rev. 3 88 freescale semiconductor mechanical data and ordering information 16.2 mechanical dimensions of the pbga package figure 77 shows the mechanical dimensions of the pbga package. figure 77. mechanical dimensions and bottom surface nomenclature of the pbga package 1. all dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m?1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. notes:
mpc885/mpc880 hardware specifications, rev. 3 89 freescale semiconductor document revision history 17 document revision history table 40 lists significant changes between revisions of this hardware specification. table 40. document revision history revision number date changes 0 02/2003 initial revision. 0.1 04/2003 added pinout and pinout assignments table. added the usb timing to section 14. added the reduced mii to section 15. removed the data parity. made some changes to the features list. 0.2 05/2003 made the changes to the rmii timing, made sure all the v ddl , v ddh , and gnd show up on the pinout diagram. changed the spi master timing specs. 162 and 164. 0.3 05/2003 corrected the signals that had overlines on them. 0.4 5/2003 changed the pin descriptions for pd8 and pd9. 0.5 5/2003 changed some more typos, put in the phsel and phreq pins. corrected the usb timing. 0.6 6/2003 changed the pin descriptions per the june 22 spec. 0.7 7/2003 added the rxclav and txclav signals to pc15. 0.8 8/2003 added the reference to usb 2.0 to the features list and removed 1.1 from usb on the block diagrams. 0.9 8/2003 changed the usb description to full-/low-speed compatible. 1.0 9/2003 added the dsp information in the features list fixed table formatting. nontechnical edits. released to the external web. 2.0 12/2003 changed the maximum operating frequency to 133 mhz. put in the orderable part numbers that are orderable. put the timing in the 80 mhz column. rounded the timings to hundredths in the 80 mhz column. put the pin numbers in footnotes by the maximum currents in table 6. changed 22 and 41 in the timing. put in the thermal numbers. 3.0 7/22/2004 added sentence to spec b1a about extclk and clkout being in alignment for integer values added a footnote to spec 41 specifying that edm = 1 added rmii1_en under m1ii_en in table 36 pin assignments added a tablefootnote to table 6 dc electrical specifications about meeting the vil max of the i2c standard put the new part numbers in the ordering information section
mpc885/mpc880 hardware specifications, rev. 3 90 freescale semiconductor document revision history this page intentionally left blank
mpc885/mpc880 hardware specifications, rev. 3 freescale semiconductor 91 document revision history this page intentionally left blank
mpc885ec rev. 3 07/2004 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution center p.o. box 5405, denver, colorado 80217 1-480-768-2130 (800) 521-6274 japan: freescale semiconductor japan ltd. technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor hong kong ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 home page: www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. learn more: for more information about freescale semiconductor products, please visit www.freescale.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004.

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